The present invention relates to a method for fabricating a metal semiconductor field effect transistor, and more particularly to a method for fabricating a GaAs metal semiconductor field effect transistor capable of reducing a resistance of a conduction channel according to a current flow and making a high-integration easier.
The prior method for a self-aligned gate (SAG) is as follows. First, a refractory metal is deposited over a substrate and a photo-resist film is coated over the refractory metal and then is subjected to a development process to pattern a gate portion. The refractory metal is over etched so as to form a self-aligned T-gate having a size smaller than a photoresist pattern using a dry etching method under a condition that the photo-resist pattern is used as a mask.
According to the prior method, on overetching the metal deposited on the substrate, it is apt to damage the substrate due to a dry etching method. And after patterning a gate, because the metal for a gate is remaining on the gate portion of the substrate, the prior method has a shortage in that it is not able to carry out a recess etching process for controlling a current of a device.
In order to solve the shortage, a self-aligned implantation for N.sup.+ layer technology SAINT has been proposed. (SAINT) for solving said shortage of SAG, comprises processes of alternately depositing and coating a silicon nitride film, a first-photo-resist film, a silicon dioxide film and a second photo-resist film, thereby forming multi-layers, patterning the second photo-resist film to form a gate pattern, etching the silicon dioxide film and the first photo-resist film using the gate pattern of the second photo-resist film as a mask, ion implanting an n-type impurity using the gate pattern of the second photo-resist film as a mask, depositing a silicon dioxide film, selectively wet-etching the silicon dioxide film, carrying out a lift-off process to expose the silicon nitride film of the gate portion, annealing for activation and forming an ohmic electrode and a gate electrode.
On exposing the gate portion, SAINT carries out a recess etching process. Since a gate is formed after annealing it is possible to select a gate metal and then deposit it. However, it has a disadvantage that the fabrication process is very complicate.